3.3 v zero delay buffer freescale semiconductor advance d clock drivers device data 501 freescale semiconductor, inc. technical data order number: mpc962304 rev 0, 07/2004 3.3 v zero delay buffer the mpc962304 is a 3.3 v zero delay buffer designed to distribute high-speed clocks in pc, workstation, datacom, telecom and other high- performance applications. the mpc962304 uses an internal pll and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. the input-to-output skew is guaranteed to be less than 250 ps and output-to-output skew is guaranteed to be less than 200 ps. features ? 1:4 outputs lvcmos zero-delay buffer ? zero input-output propagation delay, adjustable by the capacitive load on fbk input ? multiple configurations, see table 1. available mpc962304 configurations ? multiple low-skew outputs ? 200 ps max output-output skew ? 500 ps max device-device skew ? supports a clock i/o frequency range of 10 mhz to 133 mhz ? low jitter, 200 ps max cycle-cycle ? 8-pin soic package ? single 3.3 v supply ? ambient temperature range: ?40 c to +85 c ? compatible with the cy2304 functional description the mpc962304 has two banks of two outputs each. the mpc962304 pll enters a power down state when there are no rising edges on the ref input. during this state, all of the outputs are in tristate. when the pll is turned off, there is less than 2 5 a of current draw. multiple mpc962304 devices can accept and distribute the same i nput clock throughout the system. in this situation, the differe nce between the output skews of two devices will be less than 500 ps. the mpc962304 is offered in two configurations. in the -1 versio n, the reference frequency is reproduced by the pll and provide d to the outputs. the mpc962304-2 provides 1/2x and 2x th e reference frequency at the output banks. mpc962304 d suffix plastic soic package case 751-06 8-pin soic top view pin configuration clka1 clka2 fbk pll /2 ref extra divider (?2) block diagram 1 2 3 4 8 7 6 5 fbk v dd clkb2 clkb1 ref clka1 clka2 gnd clkb1 clka2 clkb2 data sheet mpc962304 idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 1
idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 2 mpc962304 3.3 v zero delay buffer netcom mpc962304 502 freescale semiconductor advanc ed clock drivers device data table 1. available mp c962304 configurations device feedback from bank a frequency bank b frequency mpc962304-1 bank a or bank b reference reference mpc962304-2 bank a reference reference/2 mpc962304-2 bank b 2 x reference reference table 2. pin description pin signal description 1 ref 1 1. weak pull-down. input reference frequency, 5 v tolerant input 2 clka1 2 2. weak pull-down on all outputs. clock output, bank a 3 clka2 2 clock output, bank a 4gnd ground 5 clkb1 2 clock output, bank b 6 clkb2 2 clock output, bank b 7 v dd 3.3 v supply 8 fbk pll feedback input table 3. maximum ratings characteristics value unit supply voltage to ground potential ?0.5 to +3.9 v dc input voltage (except ref) ?0.5 to v dd +0.5 v dc input voltage ref ?0.5 to 5.5 v storage temperature ?65 to +150 q c junction 150 q c static discharge voltage (per mil-std-883, method 3015) >2000 v
idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 3 mpc962304 3.3 v zero delay buffer netcom mpc962304 freescale semiconductor advance d clock drivers device data 503 table 4. operating conditions for mp c962304-x industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 85 q c c l load capacitance, below 100 mhz 30 pf load capacitance, from 100 mhz to 133 mhz 15 pf c in input capacitance 1 1. applies to both ref clock and fbk. 7pf table 5. electrical characte ristics for mpc962304-x industrial temperature devices 1 1. all parameters are spec ified with loaded outputs. parameter description test conditions min max. unit v il input low voltage 0.8 v v ih input high voltage 2.0 v i il input low current v in = 0 v 50.0 p a i ih input high current v in = v dd 100.0 p a v ol output low voltage 2 2. parameter is guaranteed by design and charac terization. not 100% tested in production. i ol = 8 ma (-1, -2) 0.4 v v oh output high voltage 2 i oh = -8 ma (-1, -2) 2.4 v i dd (pd mode) power down supply current ref = 0 mhz 25.0 p a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd 45.0 ma unloaded outputs, 66-mhz ref (-1, -2) 35.0 ma unloaded outputs, 35-mhz ref (-1, -2) 20.0 ma
idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 4 mpc962304 3.3 v zero delay buffer netcom mpc962304 504 freescale semiconductor advanc ed clock drivers device data table 6. switching character istics for mpc962304-x indu strial temperature devices 1 1. all parameters are spec ified with loaded outputs. parameter name test conditions min typ max unit t 1 output frequency 30-pf load, all devices 10 100 mhz output frequency 15-pf load, all devices 10 133.3 mhz duty cycle 2 = t 2 y t 1 (-1, -2) 2. parameter is guaranteed by design and char acterization. not 100% tested in production. measured at 1.4 v, fout = 66.66 mhz 30-pf load 40.0 60.0 % duty cycle 2 = t 2 y t 1 (-1, -2) measured at 1.4 v, fout < 50.0 mhz 15-pf load 45.0 55.0 % t 3 rise time 2 (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load 2.50 ns rise time 2 (-1, -2) measured between 0.8 v and 2.0 v, 15-pf load 1.50 ns t 4 fall time 2 (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load 2.50 ns fall time 2 (-1, -2) measured between 0.8 v and 2.0 v, 15-pf load 1.50 ns t 5 output to output skew on same bank (-1, -2) 2 all outputs equally loaded 200 ps output bank a to output bank b skew (-1) all outputs equally loaded 200 ps output bank a to output bank b skew (-2) all outputs equally loaded 400 ps t 6 delay, ref rising edge to fbk rising edge 2 measured at v dd /2 0 250 ps t 7 device to device skew 2 measured at v dd /2 on the fbk pins of devices 0 500 ps t j cycle to cycle jitter 2 (-1) measured at 66.67 mhz, loaded outputs, 15-pf load 180 ps measured at 66.67 mhz, loaded outputs, 30-pf load 200 ps measured at 133.3 mhz, loaded outputs, 15 pf load 100 ps t j cycle to cycle jitter 2 (-2) measured at 66.67 mhz, loaded outputs 30-pf load 400 ps measured at 66.67 mhz, loaded outputs 15-pf load 380 ps t lock pll lock time 2 stable power supply, valid clocks presented on ref and fbk pins 1.0 ms
mpc962304 freescale semiconductor advance d clock drivers device data 505 applications information figure 1. outpu t-to-output skew t sk(o) figure 2. static phase offset test reference figure 3. output duty cycle (dc) v cc v cc y 2 gnd v cc v cc y 2 gnd t 6 cclk fb_in the pin-to-pin skew is defined as th e worst case difference in propagation delay between any similar delay path within a single device v cc 1.4 v gnd v cc 1.4 v gnd t 5 the time from the pll controlled edge to the non-controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc 1.4 v gnd t 2 t 1 dc = t 2 /t 1 x 100% figure 5. cycle-to-cycle jitter t 4 t 3 v cc = 3.3 v 2.0 0.8 figure 6. output transition time test reference the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t j = | t n ?t n+1 | t n+1 figure 4. device-to-device skew v cc v cc y 2 gnd v cc v cc y 2 gnd t 7 device 1 device 2 idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 5 mpc962304 3.3 v zero delay buffer netcom
idt? 3.3 v zero delay buffer freescale timing solutions organization has been acquired by integrated device technology, inc mpc962304 6 mpc962304 3.3 v zero delay buffer netcom mpc962304 506 freescale semiconductor advanc ed clock drivers device data ordering information (available) ordering code package name package type mpc962304d-1 d8 8-pin 150-mil soic MPC962304D-1R2 d8 8-pin 150-mil soic ? tape and reel mpc962304d-2 d8 8-pin 150-mil soic mpc962304d-2r2 d8 8-pin 150-mil soic ? tape and reel 0.1 p f 0.1 p f clk out c load v dd v dd outputs gnd gnd test circuit #1 test circuit for all parameters
mpc962304 3.3 v zero delay buffer netcom ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 innovate with idt and accelerate your future networks. contact: www.idt.com part numbers insert product name and document title netcom
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